Decima-8: An Architecture That Wants to Reinvent Neuromorphic Chips

Neuromorphic computing has for years been one of the most promising and, at the same time, most frustrating areas of microelectronics. The idea is simple and appealing: build chips that work on the principles of the biological brain and get computation that is orders of magnitude more energy efficient. In practice, every attempt runs into the same walls. The Decima-8 architecture aims to move those walls, if not knock them down, and it works on several fronts at once.

To understand what Decima-8 proposes, it helps to look at the nature of the problems. Modern spiking neural networks encode information in binary: a neuron either "fires" or it doesn't. To convey gradations of a signal, without which no remotely complex computation is possible, designers have to resort to rate coding, stretching a single value across many clock cycles, or to increasing the number of physical transmission lines.

Both approaches eat up time and die area. A hardware problem exists in parallel. Memristor crossbars, which look like an ideal substrate for neuromorphic computing on paper, suffer in practice from noise, parameter drift and non-determinism.

Every chip requires individual calibration, which makes mass production a nightmare for engineers. Meanwhile, traditional Network-on-Chip designs consume up to forty percent of die area on routers, and around seventy percent of energy goes not to computation but to moving data between blocks.

Decima-8 attacks both problems at once with three key innovations. The first is the Level16 format. Instead of a binary spike, each line carries an activation level from zero to fifteen in a single clock cycle. Sixteen gradations are a deliberate compromise between the coarseness of binary representation and the temperamental nature of analog continuity. Four bits per value are enough to convey a meaningful signal gradient, while the system stays fully digital and deterministic. There is no need to spend dozens of cycles on rate coding a single number: the value is transmitted instantly.

The second innovation is digital crossbars that emulate the behavior of memristor arrays but lack their key drawbacks. No noise, no drift, no individual calibration. Every chip behaves identically, and every computation is reproducible. This sounds like a step backward: giving up "true" analog neuromorphism in favor of digital emulation. But in engineering, pragmatism often beats elegance. Memristors are beautiful in theory and painful in manufacturing. Decima-8's digital crossbars sacrifice theoretical beauty for practical workability.

The third and perhaps most radical solution is relay activation. Instead of traditional packet routing, where data travels between compute tiles through a network of routers, Decima-8 propagates activation through a dependency graph. Tiles do not "talk" to each other in the usual sense: activation simply flows from one compute block to the next along a predefined graph. This makes it possible to eliminate on-chip routers entirely. Zero percent of die area on routers is a figure that sounds almost provocative next to the standard forty percent. Fixed latency instead of the unpredictable latency of a packet network is not merely an optimization; it is a qualitatively different model of computation.

It is important, however, to keep a sober view. The architecture is so far described only at the conceptual level, and a huge distance lies between an elegant diagram and working silicon. Sixteen activation levels are fine for a certain class of tasks, but for many modern machine learning models even eight-bit quantization is considered aggressive. The question of scaling relay activation to graphs with billions of nodes remains open. Digital crossbars solve the determinism problem but may lose to analog solutions on energy efficiency, which is precisely the main promise of neuromorphic computing.

Still, Decima-8 deserves attention as a conceptually coherent attempt to rethink neuromorphic architecture as a whole rather than piece by piece. The industry has spent too long trying to solve the encoding problem separately from the communication problem and separately from the problem of hardware implementation. The "everything at once" approach is risky, but if even some of the claimed characteristics are confirmed in hardware, it could set a new direction for an entire generation of neuromorphic processors. In a world where data center energy consumption is becoming a geopolitical issue, any architecture that can radically cut the energy cost of computation deserves close study.